1. Field of the Invention
The present invention relates to a power device control circuit and more specifically, relates to a power device control circuit that enters a gate driving signal into a gate terminal of a power device.
2. Description of the Background Art
For drive of a power device such as an IGBT, a power device control circuit controls a gate signal of the power device to perform switching of the power device.
During turn-on of the power device, transition from OFF condition to ON condition of the power device involves turn-on time. This turn-on time is time required for electrical charges to be accumulated in a gate-to-emitter capacitance and a gate-to-collector capacitance. In response to charging of these capacitances, a gate voltage is increased to reach a threshold voltage, thereby placing the power device in ON condition.
There is a period when a gate-to-emitter voltage is constant during increase of the gate-to-emitter voltage. This period is called a mirror period when the gate-to-collector is charged. After elapse of the mirror period, the gate-to-emitter voltage starts to increase again to reach the threshold voltage.
It is preferable that the turn-on time have the shortest possible length in consideration of energy loss caused by switching loss. Shortening the turn-on time necessitates shortening of the aforementioned mirror period. The power device can be turned on while the mirror period is shortened by increasing a current and a voltage to be applied to a gate.
However, increasing a current and a voltage to be applied to the gate during switching increases EMI (electromagnetic interference) noise, resulting in the fear of adverse effect on a peripheral device and the like.
As described above, it is difficult to achieve both suppression of switching loss and suppression of EMI noise. So, conventionally exerted control is intended to reduce EMI noise at the expense of switching loss.
According to known technique responsive to this problem, reduction in EMI noise and reduction in switching loss are both achieved by monitoring the gate voltage of a power device during switching of the power device, and changing a gate resistance in response to the rate of change of a gate-to-emitter voltage (see Japanese Patent Application Laid-Open No. 2007-166655). Japanese Patent Application Laid-Open No. 2007-166655 exerts control to change the resistance value of the gate resistance during a mirror period to a value lower than that determined at the start of turn-on. This causes a small current to flow into a gate in the initial stage of the turn-on to reduce noise such as EMI noise, while changing a current to flow into the gate to a large current in the mirror period when noise is less likely to be generated, thereby achieving both shortening of switching time and noise reduction.
In the instant specification, a gate-to-emitter voltage is hereinafter simply called a gate voltage.
The aforementioned technique of Japanese Patent Application Laid-Open No. 2007-166655 requires a circuit to monitor the gate voltage and a circuit to protect the previous circuit from a surge voltage and the like, leading to the problems of scale increase of a control circuit and cost increase.
Control to monitor the gate voltage and feed the gate voltage back to the control circuit involves a certain period of time for the feedback, making it impossible to respond to high-speed switching.